A typical eNVM integration flow produces a structure including a non-volatile gate stack along with high-voltage and logic gate stacks. Generally, the non-volatile gate stack is constructed with an oxide-nitride-oxide (ONO) stack in between two polysilicon layers, while the high-voltage and logic gate stacks are built with a single polysilicon layer, resulting in a step height difference between the upper surface of the non-volatile gate stack and the upper surfaces of the other gate stacks. As shown in FIG. 1, a version of a structure resulting from an eNVM integration scheme includes a substrate 101 with shallow trench isolation (STI) regions 103, source/drain regions 105, a non-volatile gate stack 107, high-voltage gate stacks 109, logic gate stacks 111, spacers 113, and various gate oxide layers 115. Non-volatile gate stack 107 includes an ONO stack 117 between two polysilicon layers 119. As discussed, because the high-voltage gate stacks 109 and the logic gate stacks 111 each include only one polysilicon layer 119, a step height difference 121 exists between the upper surface of the non-volatile gate stack 107 and the upper surfaces of the high-voltage and logic gate stacks 109 and 111, respectively.
In a conventional replacement metal gate (RMG) high-k/metal gate (HKMG) integration scheme, two chemical-mechanical polishing (CMP) steps are utilized. The first CMP step is performed prior to removing dummy polysilicon gate stacks, and the second CMP step is performed after the deposition of the HKMG gate stacks is complete. These two CMP steps require that the upper surfaces of the gate stacks be coplanar. Since the usual eNVM integration flow produces a step height difference 121 between the upper surface of the non-volatile gate stack 107 and the upper surfaces of the high-voltage and logic gate stacks 109 and 111, the eNVM integration flow is incompatible with an RMG HKMG integration scheme.
A need therefore exists for eNVM and RMG HKMG compatible integration schemes, and enabling methodology.